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VCO-Based ADC With Digital Background Calibration in 65nm CMOS
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Fundamental limits on energy efficiency performance of VCO-based ADCs
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Sub-picosecond-jitter clock generation for interleaved ADC with Delay-Locked-Loop in 28nm CMOS
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Sub-Picosecond Jitter Clock Generation for Time Interleaved Analog to Digital Converter
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