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Circuit Design for Realization of a 16 bit 1MS/s Successive Approximation Register Analog-to-Digital Converter
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All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters
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A 16-b 10Msample/s Split-Interleaved Analog to Digital Converter
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Split Cyclic Analog to Digital Converter Using A Nonlinear Gain Stage
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Real-Time Software-Defined-Radio Implementation of Time-Slotted Carrier Synchronization for Distributed Beamforming
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"Applying the ""Split-ADC"" Architecture to a 16 bit, 1 MS/s differential Successive Approximation Analog-to-Digital Converter"
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Round-Trip Time-Division Distributed Beamforming
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Design of Tunable Low-Noise Amplifier in 0.13um CMOS Technology for Multistandard RF Transceivers
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Real-Time Software-Defined-Radio Implementation of a Two Source Distributed Beamformer
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Cryptography for Ultra-Low Power Devices
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