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Feng, Yu
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Disjunction of Regular Timing Diagrams
Keyword:
disjunction
,
timing diagrams
,
model checking
,
temporal logic
, and
Alloy
Creator:
Feng, Yu
Advisor:
Fisler, Kathryn
Publisher:
Worcester Polytechnic Institute
Date Created:
2010-10-12
Resource Type:
Thesis
Degree:
MS
Unit (Department):
Computer Science
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Collections
Masters Theses
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Year
2010
1
Creator
Feng, Yu
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1
Advisor
Fisler, Kathryn
1
Contributor
Fisler, Kathryn
1
Unit (Department)
Computer Science
1
Publisher
Worcester Polytechnic Institute
1
Resource type
Thesis
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