Index Catalog // Hyrax

Filter löschen

Filtern nach: Advisor McNeill, John A. Sponsor sim Allegro MicroSystems LLC

Sub-Picosecond Jitter Clock Generation for Time Interleaved Analog to Digital Converter

Stichwort:

Jitter, Clock Generation, Delay Line, Delay-Locked Loop, and Interleaved ADC

Schöpfer:

Gong, Jianping

Advisor:

McNeill, John A.

Herausgeber:

Worcester Polytechnic Institute

Datum erstellt:

2019-08-08

Resource Type:

Dissertation

Degree:

PhD

Unit (Department):

Electrical & Computer Engineering