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Sub-Picosecond Jitter Clock Generation for Time Interleaved Analog to Digital Converter
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"Applying the ""Split-ADC"" Architecture to a 16 bit, 1 MS/s differential Successive Approximation Analog-to-Digital Converter"
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A 12-b 50Msample/s Pipeline Analog to Digital Converter
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Split Non-Linear Cyclic Analog-to-Digital Converter
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All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters
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Split Cyclic Analog to Digital Converter Using A Nonlinear Gain Stage
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Adaptive Suppression of Interfering Signals in Communication Systems
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Lookup-Table-Based Background Linearization for VCO-Based ADCs
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A Highly Digital VCO-Based ADC With Lookup-Table-Based Background Calibration
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External Coil for MR Imaging of the Prostate
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