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FPGA-Based Co-processor for Singular Value Array Reconciliation Tomography

Stichwort:

hardware accelerator, FPGA, digital signal processing, and SVD

Schöpfer:

Coyne, Jack W

Advisor:

Duckworth, R. James

Herausgeber:

Worcester Polytechnic Institute

Datum erstellt:

2007-09-05

Resource Type:

Thesis

Degree:

MS

Unit (Department):

Electrical & Computer Engineering