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Background Calibration of a 6-Bit 1Gsps Split-Flash ADC Public

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In this MS thesis, a redundant flash analog-to-digital converter (ADC) using a ``Split-ADC' calibration structure and lookup-table-based correction is presented. ADC input capacitance is minimized through use of small, power efficient comparators; redundancy is used to tolerate the resulting large offset voltages. Correction of errors and estimation of calibration parameters are performed continuously in the background in the digital domain. The proposed flash ADC has an effective-number-of-bits (ENOB) of 6-bits and is designed for a target sampling rate of 1Gs/s in 180nm CMOS. The calibration algorithm described has been simulated in MATLAB and an FPGA implementation has been investigated.

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  • English
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  • etd-011013-081923
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  • 2013
Date created
  • 2013-01-10
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Permanent link to this page: https://digital.wpi.edu/show/2v23vt494