Etd

A 12-b 50Msample/s Pipeline Analog to Digital Converter

Público

Contenido Descargable

open in viewer

This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC has been realized in a 0.6um digital CMOS process. The architecture is based on a 1.5-b per stage structure utilizing digital correction for the first six stages. A differeintial switched capacitor circuit consisting of a cascode gm-c op-amp with 250MHz of bandwidth is used for sampling and amplification in each stage. Comparators with an internal offset voltage are used to implement the decision levels required for the 1.5-b per stage structure. Correction of the pipeline is accomplished by measuring the offset and gain of each of the first six stages using subsequent stages. The measured values are used to calculate digtal values the compensate for the inaccuracies of the analog pipeline. Corrected digital values for each stage are stored in the pipeline and used to create corrected output codes. Errors caused by measuring the first six stages using uncalibrated stages are minimized by using extra switching circuitry during calibration.

Creator
Colaboradores
Degree
Unit
Publisher
Language
  • English
Identifier
  • etd-0505100-104750
Palabra Clave
Advisor
Committee
Defense date
Year
  • 2000
Date created
  • 2000-05-05
Resource type
Rights statement

Las relaciones

En Collection:

Elementos

Elementos

Permanent link to this page: https://digital.wpi.edu/show/tt44pm891