The project presents a memory arbiter system capable of allowing two systems to communicate to the same DDR3 SDRAM memory. The arbiter was designed using Verilog, implemented using Xilinx Integrated Software Environment (ISE) and validated using iSim and ChipScope. The final design is implemented on a Virtex 6 FPGA chip. The arbiter can achieve a maximum performance of around 50 Gb/s, with the two systems reaching transfer rates of 25 Gb/s.

• This report represents the work of one or more WPI undergraduate students submitted to the faculty as evidence of completion of a degree requirement. WPI routinely publishes these reports on its website without editorial or peer review.

Creator

• Fischer, Laura F
• Pyatnychko, Yura

Publisher

• Worcester Polytechnic Institute

Identifier

• E-project-031212-183607

Advisor

• Huang, Xinming
• McNeill, John A.

Year

• 2012

Sponsor

• Teradyne

Date created

• 2012-03-12

Resource type

• Major Qualifying Project

Major

• Electrical & Computer Engineering

Rights statement

• In Copyright