Formal Verification of ASIC Design Public
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The goal of this project is to use a formal verification tool that checks all functionality of the RTL and GTL code to prove they are equivalent to one another. This check covers 100% of all the functions inside the code which is known as formal equivalence check. The Mentor FormalPro tool allows for easy debugging with the use of a built in GUI and several types of reports that provide information on errors within the code. This project is sponsored by PLSense Ltd. which is based in Yokneam, Israel that provide IoT SoC design to achieve minimum energy operation for the targeted performance in a wide range of frequencies.
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