Modeling the Instantaneous Power Consumption of an FPGA

Gualdarrama, Jon P

Student Work

Modeling the Instantaneous Power Consumption of an FPGA

Public

The power consumption of an FPGA’s routing network dominates the instantaneous power consumption of the device. A model for the routing network would therefore be useful for simulating the instantaneous power of the device. The goal of this project is to develop such a model, relating the power consumption of the routing network to the length of each net. This model will be integrated with power simulation tools in the Power Side-Channel Attack Risk Evaluator (PSCARE) to give a more accurate power simulation for FPGAs. Preliminary testing on the model shows that it can correctly simulate a modified PSCARE power simulation.

This report represents the work of one or more WPI undergraduate students submitted to the faculty as evidence of completion of a degree requirement. WPI routinely publishes these reports on its website without editorial or peer review.

Creator