Student Work

Design of a 16-bit 10MHz pipeline ADC using the split-ADC architecture in 0.25u CMOS

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The design of a 16-bit 10MHz pipelined Analog to Digital Converter (ADC) using the Split ADC architecture is discussed. This paper Work includes system level and circuit level simulations of the analog subsystem, and future work to be done.

  • This report represents the work of one or more WPI undergraduate students submitted to the faculty as evidence of completion of a degree requirement. WPI routinely publishes these reports on its website without editorial or peer review.
Creator
Publisher
Identifier
  • 07D021M
Advisor
Year
  • 2007
Date created
  • 2007-01-01
Resource type
Major
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