Student Work

Parallel implementation of the advanced encryption standard on field programmable gate arrays

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The desire for faster, more powerful processing hardware has always existed. However, with embedded systems, power, energy and space utilization must also be considered. Recent advances in FPGAs allow designers a means for building single chip multiprocessor systems. The focus of this MQP was to examine the execution of the AES encryption algorithm on 3 different multiprocessor configurations: multiple-program multiple-data single-program multiple-data, and multiple-program multiple-data with shared memory. Specifically, the speed, throughput and resource utilization were compared and evaluated.

  • This report represents the work of one or more WPI undergraduate students submitted to the faculty as evidence of completion of a degree requirement. WPI routinely publishes these reports on its website without editorial or peer review.
Creator
Publisher
Identifier
  • 06C039M
Advisor
Year
  • 2006
Date created
  • 2006-01-01
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