The primary goal of this project is to identify the fiberflow paradigm of processor organization as a new model for the design of high performance CPUs. The fiberflow model incorporates a number of concepts aimed at maximizing the average instruction throughput rate achievable by the processor, such as on-chip multithreading and data access/execution decoupling. To test the suitability of this approach a prototype fiberflow architecture was defined and simulated.
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