Random finite-state automata for model checkingPublic
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Formal verification has been very successful in hardware design, and its extension to software is hindered by the large finite-state automata models of modern programs. To provide a basis upon which to evaluate and improve verification algorithms, our software generates random finite-state automata with imposed structural constraints. These constraints are controlled by four different algorithms which can additionally be composed. In order to enable verification algorithm evaluations, the software exports generated finite-state automata as modules in the Verilog language which can be loaded into a model checker called VIS.
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