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Filtering by: Contributor Doroz, Yarkin Creator Adiletta, Matthew J. Unit (Department) Electrical & Computer Engineering

A Reinforcement Learning Approach To Optimize the MLC Prefetcher Aggressiveness at Run-Time

Keyword:

Computer Architecture, Mid-Level Cache Prefetchers, Run-Time Performance Tuning, Q-learning, Reinforcement Learning, and Hardware Optimization

Creator:

Adiletta, Matthew J.

Advisor:

Sunar, Berk, Shue, Craig A., and Doroz, Yarkin

Publisher:

Worcester Polytechnic Institute

Date Created:

2021-05-06

Resource Type:

Thesis

Degree:

MS

Unit (Department):

Electrical & Computer Engineering